Deformation behaviour of interconnect encapsulated on functionally graded stretchable substrates

Abstract

This work proposes an innovative design approach for a stretchable electronics substrate. The primary purpose of the substrate is to establish equilibrium among various elements that may lead to stretch-induced harm, such as plastic strain, out-of-plane deformation, and interfacial delamination. It accomplishes this by enabling the interconnect to flex with minimal resistance from the enclosed interconnect while undergoing stretching. We have utilised the dependency of PDMS with the cross-linking agent (CLA) and curing time during the fabrication process. A fabrication process using a spinning method of the functionally graded PDMS stretchable (FGPS) substrates is demonstrated so that it can be perfect cross-linking diffusion between layers with the desired thickness. Experiments indicated that curing time between poring layers is crucial in fabricating the FGPS. Further, numerical simulation was performed to examine FGPS substrates with the help of encapsulated horseshoe interconnect deformation behaviour, and results were validated with in-situ experimental results. For the numerical simulation to assign the different crosslinking PDMS properties, hyperelastic materials modelling (HMM) was done using different models to predict the behaviour of PDMS X:Y materials accurately under stretching conditions and found that (under 50% stretching) match well with R2&gt

0.99. The computational findings demonstrate that incorporating a FGPS substrate, horseshoe interconnects increase out-of-plane deformation and geometric opening, leading to a decrease in plastic strain in the interconnect by up to 32%. However, the shear strain at the substrate interconnects interfaces increased from 55.38% to 77.7%. The shear strain counter is well-matched with the observed experimental delamination locations. This substrate design approach provides customized material properties at the substrate interconnect interface to meet specific requirements and can delay the interconnect failure. © 2023 Elsevier Ltd